Overview
Sofics delivers specialty I/Os and ESD protection circuits designed to safeguard and enhance the core performance of integrated circuits. The company offers silicon-proven, standard process-compatible IP solutions for semiconductor companies, with partnerships supporting applications in photonic systems and MEMS microphone technology.
In the news
- Last week the monthly lunch & learn session at Sofics was a rehearsal, a dry-run to prepare for the big stage. In 2 weeks, we will present our work live at the TSMC OIP forum in Santa Clara (September 23) and later also in Japan (November 6). The topic: Detecting potential reliability issues in over-voltage tolerant interface circuits in advanced FinFET processes. In such high voltage I/O circuits designers use a stacked or cascoded configuration to distribute the voltage across multiple transistors. It is important to make sure the
- A design can be DRC and LVS clean and still fail after layout. During our webinar with EDA Solutions Limited, we shared two examples from our own designs: A 22nm GPIO that stopped switching in certain corners because of the well proximity effect. Both designs worked at schematic level. The problems only became visible after layout extraction and post-layout simulation. The article explains what caused these issues, how we fixed them and how Calibre and Solido helped us trace the difference between schematic intent and the extracted
- Looking for I/O or ESD IP for your next chip? You can now browse our datasheets directly on the Sofics website! We’ve added a selection of our existing IP, including specialty GPIOs, local ESD clamps and power clamps across advanced process technologies. You can search by foundry, node, voltage, GPIO, ESD and more to quickly find something relevant to your requirements. And what you see online is only a selection of what we have available. If you don’t find exactly what you need, there’s a good chance we already have something close
- It is quite fascinating that the technology we develop here at Sofics is embedded in billions of chips worldwide. Our IP is trusted by more than 150 companies and is proven across +10 different foundries. But we aren't finished yet. We are looking for a Business Development Manager to take this impact to the next level. We aren't looking for a traditional salesperson, but a technically-minded strategist who can bridge the gap between complex engineering and global market needs. If you love building markets in Europe, China, or Korea
- Pleased to welcome SOFICS to SpeakSoon. Bart Keppens, Chief Business Development at Sofics, relies on SpeakSoon to capture every conversation he has at events, from a booth in the US to an event floor in Asia. His role depends on building trust with the people he meets, not managing admin afterwards, and that's exactly the gap SpeakSoon closes for him. Event recommendations are next on the roadmap, helping him decide which show to attend before booking the ticket. With SpeakSoon, sales people like Bart can travel the world
- A record number of attendees joined the HotChips conference in Palo Alto this year, including Bart Keppens. The conference is THE place where IC designers present their latest work on high performance compute memory and AI chips on the most advanced process nodes. Not concepts, ideas or roadmaps but actual products. A great event to meet with customers to discuss what's next on their plate.
- Can we really trust standard lab tests? In semiconductor design, we rely heavily on Transmission Line Pulse (TLP) testing to ensure our components are robust. But there’s a catch: standard tests don't always capture the full picture of what happens during real-world Electrical Overstress (EOS). This is the exact challenge Olivier Mertens is tackling during his internship with us. Olivier is diving deep into the data to benchmark EOS performance against traditional TLP metrics. By systematically measuring different technology
- Stan Bettens’s internship is structured into two main research and design phases. The first part of his project focuses on the design of a proprietary voltage regulator within a specific technology, including an assessment of its compatibility for use in an ESD rail clamp. In the second part, Stan is conducting a comparative study between this proprietary regulator and a standard industry regulator. The goal of this study is to identify and analyze the performance specifications that are most critical to the industry. #Internship
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