Overview
Sofics delivers specialty I/Os and ESD protection circuits designed to safeguard and enhance the core performance of integrated circuits. The company offers silicon-proven, standard process-compatible IP solutions for semiconductor companies, with partnerships supporting applications in photonic systems and MEMS microphone technology.
Key people
In the news
- A busy week in Shanghai! From October 19 to 23, Koen Decock and Emil B. Hågan were in China for a week of meetings and technical discussions. We covered quite a few topics, from our BCD solutions to specialty I/Os, with a lot of interest in overvoltage-tolerant (OVT) and high-speed applications. It was interesting to hear the different challenges companies are working on and discuss where our technology could make a difference. It was also Koen's first time in China, so we made sure to experience a bit of Shanghai outside
- Connecting the Dutch and Flemish semiconductor ecosystems! On October 12, Sofics joined a networking event at the Embassy of the Netherlands in Brussels, welcoming a delegation of Dutch semiconductor companies and organizations. An interesting evening of exchanging insights, strengthening connections and exploring opportunities for cross-border collaboration in the semiconductor industry. Many thanks to the Embassy of the Netherlands, ChipNL Competence Centre and Flanders Semiconductors for bringing both ecosystems
- A little behind the scenes… 🎬 Something is in the making! Curious to see the result? Stay tuned! 👀
- How do you catch safe operating area (SOA) violations in over-voltage-tolerant GPIOs on advanced FinFET nodes? Our colleague Bart Keppens will explore this in his presentation at the TSMC OIP event in Japan, November 6. Sofics engineers have developed GPIOs in advanced FinFET nodes that can tolerate higher voltage. We use a Siemens EDA flow to detect and prevent Safe Operating Area violations in such designs. #Sofics #SiemensEDA #SemiconductorDesign #FinFET #GPIO
- Always nice to catch up with familiar faces! On Thursday, October 15, Johan Van der Borght and Emil B. Hågan attended GlobalFoundries Technology Summit (GTS 2026) in Munich. We had some interesting discussions about analog front-end (AFE) and ESD co-design, where minimizing parasitic capacitance is critical for signal performance. We also discussed our low-leakage and area-efficient ESD solutions, helping designers reduce leakage current and silicon footprint while meeting ESD protection requirements. Good to reconnect with
- From a lunch & learn at Sofics to a Customer’s Choice Award in Santa Clara! A few weeks ago, Bart Keppens was rehearsing his presentation in front of colleagues at our monthly lunch & learn. On September 23 he took that presentation to TSMC OIP North America in Santa Clara. And he came back with an award! Together with Mohamed Atoua and John Peloso from Siemens EDA (Siemens Digital Industries Software), we worked on detecting reliability issues in over-voltage-tolerant GPIOs at advanced TSMC nodes. The presentation showed how the
- Koen our Head of Analog Engineering and Emil will be in China from Monday 19 October to Friday 23 October. We’ll be meeting with semiconductor companies to discuss where Sofics can help with specialty I/O, on-chip ESD protection and analog front-end solutions. From extending interface voltage options to solving specific ESD and analog design challenges, these discussions are often where interesting new projects start. #Semiconductors #ESD #AnalogDesign #ICDesign
- The best collaborations start with being open about where one team’s expertise ends and another’s begins. That is what makes our collaboration with Alcyon Photonics work. Alcyon brings proven photonic IP and deep PIC design expertise. Sofics brings specialized EIC interface IP, including low-capacitance ESD protection and reliability solutions. By working together early, we can help customers close the gaps between the photonic and electronic sides of their design. This means fewer late surprises, less integration risk and
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