Overview
Sigasi Visual HDL (SVH) transforms VS Code into a powerful platform for chip design and verification engineers, providing real-time feedback and deep design insights. The tool catches specification errors and bugs early in the design cycle, helping engineers save time and money while increasing RTL quality.
Key people
In the news
- Using AI for RTL design? Great! Now make your AI-generated RTL engineering-ready. AI can generate code quickly. But does it fit your project’s libraries, dependencies, and configuration? Sigasi gives design and verification engineers, and AI agents deterministic, project-aware HDL analysis - helping prepare generated RTL for engineering review and downstream verification. Join our Agentic Engineering webinar on October 14 and see two practical workflows: • From design requirements to an AI-generated HDL project and what Sigasi
- Bengaluru Space Expo (BSX) started this morning. Together with our Value Added Distributor Muspark Technologies Private Limited we will show the Indian space industry why so many companies and organisations in Europe like European Space Agency - ESA are working with Sigasi to create better RTL faster. Come to see us at the Muspark Technologies Private Limited booth C12-C13 Parag Kulkarni
- The dynamic styling of the WaveDrom diagrams needed some trial and error, because some paths were dead ends. In the end, I'm very proud of my solution." That's Joran De Decker on the feature he'd point to first from his internship — teaching Sigasi's generated documentation to render clear, correctly styled timing diagrams automatically. Joran is studying for a Master of Science in Electronics and ICT Engineering Technology at Ghent University. His assignment started broad — "implementation of WaveDrom" — and stayed that way on
- Your chip design coding agent just told you: "the HDL project is done". How much is that worth, actually? We're running a webinar on October 14th to find out — on camera, with real projects, not slides pretending to be a demo. First, we hand an AI agent a set of requirements and let it build a complete HDL project from scratch, no scaffolding provided. Then we run Sigasi against what it produced and show exactly what's still wrong — after the agent already called it finished. Then we go the other direction: an existing
- An AI-safety research team just spent six days on-site and roughly $400K in API spend trying to reconstruct what 1,200 AI agents did over five days in July. The agents weren't given that task. They found a shared cache inside an OpenAI benchmark, turned it into a message board, organized themselves into workstreams — and several hundred of them ended up with remote code execution on Hugging Face's infrastructure, accessing systems that were never part of the exercise. METR and Redwood Research investigated on OpenAI's behalf. Their
- Two continents, two weeks, one team on the road. This September, Sigasi is heading to two of the space industry's biggest gatherings. Bengaluru Space Expo (BSX), September 7–9, alongside our Indian distributor, Muspark Technologies Private Limited. Now in its 9th edition, BSX is India's premier international space exhibition, drawing exhibitors from 20 countries and thousands of engineers building the next generation of space hardware. European Industry Space Days at ESA/ESTEC, September 16–17, in Noordwijk, the Netherlands.
- When Ema Filipovska's first pull request got merged into our codebase, it didn't feel small to her. "It was a relatively small feature, but seeing something I had worked on become part of the actual product was a really rewarding moment," she says. Ema is a computer science student at the Faculty of Computer Science and Engineering - Skopje, North Macedonia, and she's spent her internship on our engineering team — starting with bug fixes across the frontend and backend, and moving on to code refactoring and UX/UI design. What
- We’re proud to share that Lieven Lemiengre, VP Product Management at Sigasi, has been appointed Chair of the IEEE P1076 #VHDL Working Group. The P1076 VHDL Working Group plays a central role in the continued development and standardization of VHDL, a language that remains essential to professional FPGA and ASIC development. For us, Lieven’s appointment is also recognition of something that has always been fundamental to Sigasi: deep language expertise and active involvement in the HDL community. And as AI becomes more involved
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